Patent · US Active

RRAM device

US9543511B2 · kind B2 · utility

15Cited by
3References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 12, 2015
Grant dateJan 10, 2017
Priority date
Expiry dateMar 12, 2035

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10N70/8833

Abstract

The present disclosure relates to an integrated circuits device having a RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect layer surrounded by a lower ILD layer and a bottom electrode disposed over the lower metal interconnect layer. The bottom electrode has a lower portion surrounded by a bottom dielectric layer and an upper portion wider than the lower portion. The bottom dielectric layer is disposed over the lower metal interconnect layer and the lower ILD layer. The integrated circuit device also has a RRAM dielectric with a variable resistance located on the bottom electrode, and a top electrode located over the RRAM dielectric. The integrated circuit device also has a top dielectric layer located over the bottom dielectric layer abutting sidewalls of the upper portion of the bottom electrode, the RRAM dielectric, and the top electrode.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.