Reducing switching error in data converters
US9543974B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 18, 2015 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Sep 18, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In some converter architectures, unary digital-to-analog (DAC) converter elements generate an analog output which represents the digital input signal. Thermometer codes trigger an appropriate number of DAC elements to generate the analog output. The DAC elements are not all perfectly weighted, and mismatch shaping is often used to dynamically equalize the usage of each DAC element during data conversion to average out the mismatches. Unfortunately, mismatch shaping adds additional switching and can worsen the effect of switching errors. Switching errors which are non-linearly dependent on the input causes a second order distortion if the sum of the switching errors corresponding to a set of DAC elements is not zero. Prior to data conversion, calibration can select a subset of DAC elements having a lesser sum of switching errors for data conversion. Other (redundant) DAC elements are not used at all or shut off permanently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.