CRC-based forward error correction circuitry and method
US9543981B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2014 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Aug 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/16
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A CRC (cyclic redundancy check) generator circuit (28) generates a first CRC code based on a message. The CRC code is amended to the message, creating a first data packet. Circuitry transforms the first data packet to a second data packet for suitable transmission. Digital receiver circuitry receives the second data packet. A CRC verification circuit compares a received digital CRC code portion of the second data packet to a calculated digital CRC code portion. A message is presented for processing if no error is detected. A CRC-based FEC (forward error correction) circuit receives the message and calculates a digital CRC code from the verification circuit. When an error is detected, the detected error, based on a determination of whether the detected error affects an even number of bits or an odd number of bits, is corrected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.