Multilevel driver for high speed chip-to-chip communications
US9544015B2 · kind B2 · utility
60Cited by
204References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 18, 2015 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Aug 18, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4917
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Transmission line driver systems are described which are comprised of multiple paralleled driver elements. The paralleled structure allows efficient generation of multiple output signal levels with adjustable output amplitude, optionally including Finite Impulse Response signal shaping and skew pre-compensation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.