Method and system for optimizing short term stability of a clock pulse
US9544078B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 2012 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Jul 28, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0667
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system for optimizing short-term stability of a clock source clock pulse synchronized with a long-term stable reference-clock transmits clock numbers of a first reference clock to the clock source, between an initialization time and several times within a data-packet network. The clock pulse is adjusted by controlling a difference between clock numbers of the first reference clock received in the clock source and clock numbers of the first reference clock between the initialization time and the reception times of the clock numbers of the first reference clock. Clock numbers of a second reference clock are transmitted to the clock source with the clock number of at least one second reference-clock source at individual times. The maximum difference between the first and the second reference clock is known. The difference between the clock pulse of the clock source and each second reference clock is limited to an adjustable threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.