Methods and apparatuses for reducing common mode failures of nuclear safety-related software control systems
US9547328B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2014 |
| Grant date | Jan 17, 2017 |
| Priority date | — |
| Expiry date | Aug 20, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system includes at least a first division and a second division. The first division has a first clock rate and the second division has a second clock rate. The computing system includes a first processor configured to execute a task on the first division and a second processor configured to execute the task of the second division. The task executed on the first division operates according to the first clock rate, and the task executed on the second division operates according to the second clock rate. A method of executing a task in order to reduce common mode failures in a computing system includes varying a program speed of each of the plurality of divisions such that the task, when executed on a corresponding one of the plurality of divisions, operates at a clock rate according to the corresponding one of the plurality of divisions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.