Interrupt supervision system, processing system and method for interrupt supervision

US9547546B2 · kind B2 · utility

Assignee

• NXP USA, Inc. · US

Inventors

• Markus Baumeister · Aachen, DE
• Jeffrey L. Freeman · Purcellville, US

Key dates

• Filing date: Mar 12, 2012
• Grant date: Jan 17, 2017
• Expiry date: Sep 14, 2032

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F13/24
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An interrupt supervision system comprises an interrupt controller device comprising a plurality of interrupt request input lines and at least one output line connectable to a processing device. The interrupt controller device is arranged to receive, on the plurality of interrupt request input lines, a plurality of corresponding interrupt requests and to provide, on the at least one output line, the plurality of interrupt requests to the processing device in a sequence generated by the interrupt controller device depending on one or more priorities assigned to the interrupt requests; and one or more interrupt checker devices, each being arranged to receive a reception indication when the interrupt controller device receives, on a selected one of the plurality of interrupt request lines, a corresponding selected interrupt request, and to provide a corresponding error indication when an output of the corresponding selected interrupt request from the interrupt controller device on the at least one output line is not confirmed within a latency period assigned to the corresponding selected interrupt request, wherein the assigned latency period begins when the interrupt checker device rec…