Resistive semiconductor memory capable of performing incremental step pulse programming (ISPP) based on digital code values of memory cells
US9548114B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2013 |
| Grant date | Jan 17, 2017 |
| Priority date | — |
| Expiry date | Oct 31, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are a semiconductor memory apparatus, a program method, and a program system. The semiconductor memory apparatus includes a memory cell array including a plurality of resistive memory cells and a control block configured to variably control, based on digital code values reflecting resistance states of the resistive memory cells, at least one of a initial voltage magnitude and an initial voltage applying time in an incremental step pulse programming (ISPP) mode for the plurality of memory cells. Therefore, even in the case of the worst cell, the incremental step of the ISPP may be minimized, and the writing time may be reduced, limiting unnecessary current consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.