Integrated circuit stack including a patterned array of electrically conductive pillars
US9548277B2 · kind B2 · utility
1Cited by
20References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2015 |
| Grant date | Jan 17, 2017 |
| Priority date | — |
| Expiry date | Apr 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer layer. The interposer layer may include at least one integrated circuit die and an interposer portion that includes a plurality of electrically conductive pillars arranged in a laterally patterned array within the interposer layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.