Method of improving bipolar device signal to noise performance by reducing the effect of oxide interface trapping centers

US9548298B1 · kind B1 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Weidong Tian · Dallas, US
• Yuguo Wang · Plano, US
• Tathagata Chatterjee · Allen, US
• Rajni J. Aggarwal · Garland, US

Key dates

• Filing date: Nov 16, 2015
• Grant date: Jan 17, 2017
• Expiry date: Nov 16, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/85

Abstract

An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.