Array substrate and method for fabricating the same
US9548324B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2014 |
| Grant date | Jan 17, 2017 |
| Priority date | — |
| Expiry date | May 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An array substrate and a method for fabricating the same are disclosed. The method includes steps of providing a substrate (20), a first metal layer including patterns of gate electrodes (21, 24) of a first and second TFTs, an active layer (27) and a gate insulation layer (28) are formed on the substrate; forming an etch stop layer film and a photoresist sequentially on the substrate (20), and allowing the photoresist to form a first, second and third regions through gray-scale exposing and developing; forming a pattern of an etch stop layer (29), a connection via hole (30), and a contact via hole (31) respectively in the first, second and third regions through a patterning process; and forming source electrodes and drain electrodes (22, 23,25, 26) of the first and second TFTs. Photoresist of different thicknesses are disposed according to etch depths, thereby avoiding the over-etch of relatively shallow via holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.