Drive for cascode stack of power FETs
US9548739B2 · kind B2 · utility
2Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2015 |
| Grant date | Jan 17, 2017 |
| Priority date | — |
| Expiry date | Mar 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/30132
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a cascode configuration that moves the gate of the cascode substantially without delay relative to an output node by capacitively coupling the latter onto the cascode gates. The passive coupling eliminates the need for actively driving the gates of the cascode. In some embodiments, the only circuitry needed on the cascode gate may be a biasing circuit that limits the swing on the cascode gate between Vmax and 2×Vmax, where Vmax is a transistor device rating.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.