High speed controllable load
US9551751B2 · kind B2 · utility
1Cited by
206References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 15, 2011 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Jun 30, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3272
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A high speed controllable load uses a voltage waveform synthesizer and a driver circuit to dynamically control an electronically variable load to generate a current though an arc fault circuit interrupter (AFCI) device under test. Sensors may be used to monitor a source voltage and the output current to generate an arbitrary waveform have a range of voltage and current phase shifts. An optical isolation circuit allows separation of grounds between a control stage and the AFCI device under test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.