Branch prediction power reduction
US9552032B2 · kind B2 · utility
1Cited by
48References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2012 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Dec 15, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a microprocessor is provided. The microprocessor includes instruction memory and a branch prediction unit. The branch prediction unit is configured to use information from the instruction memory to selectively power up the branch prediction unit from a powered-down state when fetched instruction data includes a branch instruction and maintain the branch prediction unit in the powered-down state when the fetched instruction data does not include a branch instruction in order to reduce power consumption of the microprocessor during instruction fetch operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.