Vector indexed memory access plus arithmetic and/or logical operation processors, methods, systems, and instructions
US9552205B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2013 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Oct 9, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor including a decode unit to receive a vector indexed load plus arithmetic and/or logical (A/L) operation plus store instruction. The instruction is to indicate a source packed memory indices operand that is to have a plurality of packed memory indices. The instruction is also to indicate a source packed data operand that is to have a plurality of packed data elements. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to load a plurality of data elements from memory locations corresponding to the plurality of packed memory indices, perform A/L operations on the plurality of packed data elements of the source packed data operand and the loaded plurality of data elements, and store a plurality of result data elements in the memory locations corresponding to the plurality of packed memory indices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.