Integrated circuit with control node circuitry and processing circuitry
US9552206B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2011 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Dec 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8053
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Traditionally, providing parallel processing within a multi-core system has been very difficult. Here, however, a system is provided where serial source code is automatically converted into parallel source code, and a processing cluster is reconfigured “on the fly” to accommodate the parallelized code based on an allocation of memory and compute resources. Thus, the processing cluster and its corresponding system programming tool provide a system that can perform parallel processing from a serial program that is transparent to a user. Generally, a control node connected to the address and data leads of a host processor uses messages to control the processing of data in a processing cluster. The cluster includes nodes of parallel processors, shared function memory, a global load/store, and hardware accelerators all connected to the control node by message busses. A crossbar data interconnect routes data to the cluster circuits separate from the message busses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.