Semiconductor memory device including non-volatile memory, cache memory, and computer system
US9552256B2 · kind B2 · utility
1Cited by
6References
18Claims
0Family size
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Key dates
| Filing date | Dec 22, 2015 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Dec 22, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.