Maintaining command order of address translation cache misses and subsequent hits
US9552304B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2015 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Aug 24, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method includes storing commands and maintaining an order of receipt of the commands in a command processing unit. The commands include address translation cache miss commands that are organized as one or more linked lists and stored in a content-addressable memory (CAM). All nodes within a single linked list include commands having addresses that map to the same hash value. Based on receiving a memory fetch completion indicator for a cache entry for a command in a head node in a linked list, all of the commands in the linked list are returned. The returning includes sending the commands in the linked list to an address translation unit in an order specified by the linked list.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.