Image sensor using backside illumination photodiode and method for manufacturing the same
US9553120B2 · kind B2 · utility
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Key dates
| Filing date | Oct 31, 2014 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Oct 31, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/809
Abstract
A technology capable of simplifying a process and securing a misalignment margin when bonding two wafers to manufacture an image sensor using backside illumination photodiodes. When manufacturing an image sensor through a 3D CIS (CMOS image sensor) manufacturing process, two wafers, that is, a first wafer and a second wafer are electrically connected using the vias of one wafer and the bonding pads of the other wafer. Also, when manufacturing an image sensor through a 3D CIS manufacturing process, two wafers are electrically connected using the vias of both the two wafers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.