On-chip vertical three dimensional microstrip line with characteristic impedance tuning technique and design structures
US9553348B2 · kind B2 · utility
1Cited by
35References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2016 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Apr 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A vertical three dimensional (3D) microstrip line structure for improved tunable characteristic impedance, methods of manufacturing the same and design structures are provided. More specifically, a method is provided that includes forming a first microstrip line structure within a back end of the line (BEOL) stack. The method further includes forming a second microstrip line structure separated from the BEOL stack by a predetermined horizontal distance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.