Multi-level power converter
US9553516B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 2, 2015 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Mar 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M1/0095
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
This is a multi-level converter comprising one or more arms (B) to each be connected between a voltage source (VDC) and a current source (I). Each arm comprises two stages (E1, E2) in cascade, the first to be connected to the voltage source (VDC), the second to be connected to the current source (I). The first stage (Et1) comprises several elementary stages (E1n, . . . , E12, E11) of rank one to n in cascade, the elementary stage (E11) of rank one being connected to the second stage (Et2) and the elementary stage (E1n) of rank n having to be connected to the voltage source (VDC). Each elementary stage (E1n) comprises a pair of identical cells of NPC type (Cen1, Cen2) in series, the connection being direct in the elementary stage of rank 1, the connection being made via n−1 capacitive cells ((Can(1), . . . , Can(n−1)) for each elementary stage of rank greater than one, the second stage (Et2) comprising a floating capacitor cell (Ce10).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.