Frequency multiplier
US9553568B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2015 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Oct 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03B19/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency multiplier includes an input terminal, an output terminal, a first transistor having a first gate to which a radiofrequency signal is input from the input terminal, a first drain from which an output signal is issued to the output terminal, and a first source, a second transistor having a second gate, a second source to which the radiofrequency signal is input from the input terminal, and a second drain from which an output signal is issued to the output terminal, and a stabilizing resistor which is a resistor connected to the second gate, wherein no resistor exists on the path for the radiofrequency signal, and wherein the stabilizing resistor suppresses a reflex gain produced by the second transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.