Solid state power controller
US9553574B2 · kind B2 · utility
1Cited by
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4Claims
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Assignee
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Key dates
| Filing date | May 21, 2015 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | May 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/165
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A solid state power controller including: a plurality of pairs of FETs connected in parallel, each pair comprising a first, forward-facing FET and a second, backward-facing FET connected by their respective sources; gate drive means for switching said FETs on and off; and means for isolating the sources of the backwards-facing FETs of the plurality of pairs of FETs from each other and operating the backwards-facing FETs in 3rd quadrant operation mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.