Filed programmable gate array device with programmable interconnect in back end of line portion of the device
US9553586B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2014 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Dec 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Field-Programmable Gate Array device is provided with programmable interconnect points in the form of interconnect circuits comprising one or more pass transistors, wherein at least some components of the interconnect circuits are implemented in the Back-End-Of-Line part of the Field-Programmable Gate Array device's production process. The memory element in an interconnect point is not produced as a Static Random Access Memory cell, but as a Dynamic Random Access Memory cell, requiring only a single select transistor and a storage capacitor for each memory element. The fabrication of at least the select transistor and the pass transistor involves the use of a thin film semiconductor layer, e.g., Indium Gallium Zinc Oxide, enabling production of transistors with low leakage in the Back-End-Of-Line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.