Techniques for reducing offsets in an analog to digital converter
US9553599B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2016 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Feb 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an example, a successive approximation register analog-to-digital converter includes a switched capacitor digital-to-analog converter (DAC) first array to sample an input signal and to convert a sample of the input signal to a digital value represented by a plurality of bits, the first array including a first group of capacitors representing at least some of the plurality of bits, a switched capacitor DAC second array including a second group of capacitors representing at least some of the plurality of bits, wherein at least one bit of the plurality of bits represented by the second group of capacitors is represented by at least two capacitors, and wherein each of the two capacitors is configured to be selectively connected to a selected one of at least two reference potentials such that the at least one bit represented by the second group of capacitors is switchable between at least three states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.