Skew detection and correction in time-interleaved analog-to-digital converters
US9553600B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2016 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Jun 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a system, circuit, and method for correcting clock skew in time-interleaved analog-to-digital converters. At least two clock signals are received along respective channels. A delay of a first channel, carrying a first clock signal, is accounted for by applying one or more first adjustment factors to the channels until an edge of the first clock signal is aligned with a transition point of a reference signal. The first clock signal is swapped to the second channel, and vice-versa. A value of the reference signal as sampled by the first clock signal is compared to values of the reference signal as sampled by the second clock signal to determine a skew of the second channel vis-à-vis the first channel, and one or more second adjustment factors are applied to the second channel based on the determined skew of the second channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.