Method and system for split voltage domain receiver circuits
US9553676B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 16, 2016 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Feb 16, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02B6/4242
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Methods and systems for split voltage domain receiver circuits are disclosed and may comprise amplifying received electrical signals in a plurality of partial voltage domains, and combining the amplified received signals, utilizing a stacked cascode amplifier for each partial voltage domain, into a single differential signal in a single voltage domain. The stacked cascode amplifiers may comprise a feedback loop having a comparator which controls a current source in each domain. The signals may be received from a photodiode, which may be integrated in the integrated circuit. The amplified signals may be combined via stacked common source or common emitter amplifiers. The received signals via may be amplified by stacked inverters. The amplified received signals may be AC or DC coupled prior to the combining. The received electrical signals may be amplified and combined via cascode amplifiers. The voltage domains may be stacked and may be controlled by feedback loops.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.