Clock tree circuit and memory controller
US9557764B2 · kind B2 · utility
0Cited by
4References
25Claims
0Family size
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Key dates
| Filing date | Dec 28, 2015 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | Dec 28, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock tree circuit Including a first clock source, generating a first signal, and a first tree circuit. The first clock tree circuit includes a first driving stage for receiving the first signal, a second driving stage, connected to the first driving stage, a third driving stage, connected to the second driving stage, and a metal connection element, coupled between different nodes of the third driving stage and configured as a short-circuited element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.