Semiconductor device for masking data stored in twin cell and outputting masked data
US9558838B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 22, 2013 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | Aug 22, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array includes a plurality of twin cells, each of the twin cells composed of a first storage element and a second storage element configured to hold binary data according to a difference in threshold voltage between them, the first storage element and the second storage element each being electrically rewritable. Upon receiving a request to read the twin cell, when the threshold voltage of the first storage element forming the twin cell is lower than an erasure determination level and the threshold voltage of the second storage element forming the twin cell is lower than the erasure determination level, an output circuit masks the data stored in the twin cell and outputs the masked data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.