Devices and methods with capacitive storage for latch redundancy
US9559671B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2015 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | Dec 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A master slave storage circuit can include a first master portion coupled to a first master data storage node and a first slave portion coupled to a first slave data storage node. The first master portion can comprise one of a first master latch or a first master capacitive element coupled to the first master data storage node and the first slave portion comprises one of a first slave latch or a first slave capacitive element coupled to the first slave data storage node. If the first master portion comprises the first master latch, the first slave portion comprises the first slave capacitive element, and if the first master portion comprises the first master capacitive element, the first slave portion comprises the first slave latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.