Phase locked loop with sub-harmonic locking prevention functionality
US9559707B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2014 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | Oct 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments relate to type-I PLLs that do not lock at a sub-harmonic frequency of a reference clock signal by controlling timing of charging or discharging of one or more capacitors in the PLLs. A phase frequency detector (PFD) of a type-I PLL can prevent sub-harmonic locking by generating a clear output signal to cause a sampling capacitor of PLL's loop filter to discharge only during a time period when the sampling capacitor is not being charged. For example, the PFD can include a gating element to control the time during which the clear output signal is generated. By ensuring that the sampling capacitor is not discharged during a time period while it is being charged, the PLL's voltage-controlled oscillator is controlled to oscillate at an intended frequency rather than at a sub-harmonic of the intended frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.