System and method for adjusting clock phases in a time-interleaved receiver
US9559877B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2015 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | Oct 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03885
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Clock timing skew may occur during operation of a time-interleaved receiver. It would be beneficial to try to determine if there is timing skew, and if there is, then address it, such as by reducing or eliminating some or all of the timing skew. Embodiments are described herein that may achieve this. In one embodiment, a method includes generating at least two clocks having the same frequency but a different phase. Intersymbol interference (ISI) values are then determined, one for each of the clocks, by: for each clock, sampling a signal using the clock and determining a value representing ISI based on the sampled signal. A clock phase of at least one of the clocks is adjusted in response to at least one of the ISI values being different from a reference ISI value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.