Testing apparatus for providing per pin level setting
US9562947B2 · kind B2 · utility
0Cited by
8References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 17, 2013 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Dec 14, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/327
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A testing apparatus for providing per pin level setting is disclosed, and the testing apparatus includes a control unit and a filter circuit, where the control unit is electrically connected to the filter circuit. The control unit includes a field programmable gate array (FPGA) for providing a PWM signal. The filter circuit receives the PWM signal and outputs at least one DC voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.