Array substrate, fabricating method thereof and display device
US9563301B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 17, 2013 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Mar 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2203/04103
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array substrate, a fabricating method thereof and a display device are provided, and the array substrate comprises: a plurality of gate lines (21), extending in a first direction; a plurality of data lines (22), extending in a second direction and crossed with the plurality of gate lines (21), and the second direction being perpendicular to the first direction; a plurality of pixel units, defined by the gate lines (21) and the data lines (22) crossed with each other and arranged to be a matrix, wherein each pixel unit comprises a pixel electrode (23), a thin film transistor (24) and a common electrode (25), wherein the common electrode (25) comprises a plurality of strip-shaped electrode strips; and at least one first sensing line (26) and at least one second sensing line (27), and the first sensing line (26) and the second sensing line (27) being disposed in an upper layer and a lower layer respectively, the first sensing line (26) being insulated from and parallel to and overlapped with the second sensing line (27), and the first sensing line (26) and the second sensing line (27) both crossed with the electrode strips of the common electrode (25), wherein the upper layer and t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.