Extensible iterative multiplier
US9563401B2 · kind B2 · utility
4Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2013 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Jun 12, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5338
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An extensible iterative multiplier design is provided. Embodiments provide cascaded 8-bit multipliers for simplifying the performance of multi-byte multiplications. Booth encoding is performed in the lowest order multiplier, with the result of the Booth encoding then provided to higher order multipliers. Additionally, multiply-add operations can be performed by initializing a partial product sum register. Configurable connections between the multipliers facilitate a variety of possible multiplication options, including the possibility of varying the width of the operands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.