Initiation of cache flushes and invalidations on graphics processors
US9563561B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2013 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Oct 16, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/302
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems may provide for receiving, at a graphics processor, a workload from a host processor and using a kernel on the graphics processor to issue a thread group for execution of the workload on the graphics processor. Additionally, one or more coherency messages may be initiated, by the graphics processor, in response to a thread-related condition of one or more caches on the graphics processor. In one example, the thread-related condition is associated with the execution of the workload on the graphics processor and indicates that the one or more caches on the graphics processor are not coherent with a system memory associated with the host processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.