Method and device for buffer processing in system on chip
US9563584B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Aug 22, 2013 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Aug 22, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are a method and device for buffer processing in a System on Chip (SoC). The method includes that when a first datum of a first user needs to be buffered, a current storage start address is read, the first datum is stored into a buffer space from the current storage start address, wherein the buffer space occupied by the first datum is a first buffer space; corresponding to the first datum, storage location information including a start address and a space length of the first buffer space is saved, so that when the first datum needs to be read, the first buffer space is located according to the start address and the space length, and the first datum is read from the first buffer space; the current storage start address is updated with a next address of the first buffer space, so that next data needing to be buffered is buffered from the updated current storage start address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.