OS bypass inter-processor interrupt delivery mechanism
US9563588B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2014 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Feb 2, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/2418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides methods and systems to allow user space applications running on different cores to efficiently communicate interrupts between each other without have to enter an OS kernel. In one aspect, a hardware device for delivering inter-processor interrupts is provided. The hardware device includes a memory having a memory space that corresponds to a virtual memory space of a first guest process and a controller coupled to the memory. The controller may be configured to detect when interrupt information is recorded in the memory space. In that regard, the interrupt information is directed to a second guest process associated with a particular CPU core. In response to detecting interrupt information recorded in the memory space, the controller is configured to cause the second guest process to run on a different CPU core without making an operating system call.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.