Methods for reducing memory space in sequential operations using directed acyclic graphs
US9563933B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2014 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Feb 8, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/4434
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various disclosed embodiments are directed to methods and systems for reducing memory space in sequential computer-implemented operations. The method includes generating a directed acyclic graph (DAG) having a plurality of vertices and directed edges, wherein each edge connects a predecessor vertex to a successor vertex. Each vertex represents one of the computer-implemented operations and each directed edge represents output data generated by the operations. The method includes merging one of the predecessor vertex with one of the successor vertex by combining the operations of the predecessor vertex and the successor vertex if the predecessor and successor vertices are connected by a directed edge and there is only one directed edge originating from the predecessor vertex. The merger of the predecessor and the successor vertices reduces the number of directed edges in the DAG, resulting in a reduction of intermediate buffer memory required to store the output data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.