Memory controller and operating method thereof
US9564239B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2016 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Mar 16, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for operating a memory controller includes: performing a hard decision read operation to read hard decision data from a memory device; if a hard decoding for the hard decision data fails, assigning log likelihood ratio (LLR) values to cells falling in a plurality of voltage regions corresponding to a plurality of read reference voltages; performing a soft decision read operation based on the LLR values and a soft decoding for the soft decision data to generate an error free data; performing a read operation to read data from the memory device using each of the plurality of read reference voltages to generate raw data for each of the plurality of read reference voltages; and determining an optimal read reference voltage among the plurality of the read reference voltages based on the raw data and the error free data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.