NOR flash device manufacturing method
US9564336B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2012 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Jul 31, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28123
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment of a NOR Flash device manufacturing method includes: providing a substrate having a first polycrystalline silicon layer disposed thereon; forming a first hard mask layer on the first polycrystalline silicon layer; etching the first hard mask layer to form a first opening, and cleaning a gas pipeline connected to an etching cavity before etching the first hard mask layer; forming a second hard mask layer on the first hard mask layer, and the second hard mask layer covers the bottom and side wall of the first opening; etching the second hard mask layer to form a second opening, the width of the second opening is smaller than the width of the first opening; etching the first polycrystalline silicon, forming a floating gate. The NOR Flash device manufacturing method improves the yield of the NOR Flash device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.