Bonding pad arrangment design for multi-die semiconductor package structure
US9564395B2 · kind B2 · utility
0Cited by
3References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2015 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Jul 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package structure includes a base. A first die is mounted on the base. The first die comprises a plurality of first pads with a first pad area arranged in a first tier. A plurality of second pads with a second pad area is arranged in a second tier. A second die is mounted on the base. The second die includes a plurality of third pads arranged in a third tier. A first bonding wire has two terminals respectively coupled to one of the first pads and one of the third pads. A second bonding wire has two terminals respectively coupled to one of the third pads and one of the second pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.