Array substrate and display device
US9564453B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Nov 23, 2012 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Mar 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136286
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate and a display device are provided, and the array substrate, comprising: a substrate; and gate lines (2) and data lines (1), formed on the substrate and configured to defining pixel units, wherein, each data line (1) is located in a middle part of a corresponding pixel unit and configured to dividing each pixel unit into a first sub-pixel unit (7) and a second sub-pixel unit (8), wherein the first sub-pixel unit (7) is connected to one thin film transistor (6) and the second sub-pixel unit (8) is connected to one thin film transistor (6) for independent charging, and the thin film transistors (6) are located in a region corresponding to the corresponding gate line. The data line (1) is arranged in the middle of the corresponding pixel unit, and the first sub-pixel unit (7) and the second sub-pixel unit (8) are connected to two individual thin film transistors (6) to be independently charged, a width of the gate line can be greatly reduced, and the aperture ratio of the pixel can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.