Area-efficient metal-programmable pulse latch design

US9564881B2 · kind B2 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Qi Ye · San Diego, US
• Steven James Dillen · San Diego, US
• Animesh Datta · San Diego, US
• Zhengyu Duan · San Diego, US
• Satyanarayana Sahu · San Diego, US
• Praveen Narendranath · San Diego, US

Key dates

• Filing date: May 22, 2015
• Grant date: Feb 7, 2017
• Expiry date: May 22, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K5/131
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A pulse generator includes a latch module for storing first/second states, a pulse clock module for generating a clock pulse, and a delay module for delaying the clock pulse at a second latch-module input. The latch module has a first latch-module input coupled to a clock, the second latch-module input, and a latch-module output. The pulse clock module has a first pulse-clock-module input coupled to the clock, a second pulse-clock-module input coupled to the latch-module output, and a pulse-clock-module output. The delay module is coupled between the latch-module output and second pulse-clock-module input or between the pulse-clock-module output and second latch-module input. The delay module provides functionally I at a delay module output, where I1 is a function of I and IA is a function of IN0 and B0, and where I is a delay module input, B0 is a first input bit, and IN0 is a first net input.