Methods and systems for clocking a physical layer interface
US9564905B2 · kind B2 · utility
2Cited by
4References
12Claims
0Family size
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Key dates
| Filing date | Oct 29, 2013 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Oct 19, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for clocking a physical layer (“PHY”) and a controller of a computing device, comprises the steps of: generating a reference clock signal; synchronizing a plurality of clock signals as a function of the reference clock signal; and clocking the controller and the PHY using the plurality of synchronized clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.