Method and circuit for delay adjustment monotonicity in a delay line
US9564909B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2015 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Sep 22, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circuit device configured for delay adjustment monotonicity and method of operating therefor. This delay circuit device is configured with hybrid coarse-fine delay cells and uses a sequence of these delay cells activated in a way that builds-up the delay as a sequence of fine steps until it reaches the coarse delay value. This configuration allows for the continuing build of propagation delay by adding the fine steps of the following delay cells. In this manner, the monotonicity of the signal delay circuit is ensured by the architecture independent from device mismatch, thus eliminating problems with conventional delay circuits such as gaps and overlaps specific the these conventional delay cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.