Synchronization of outputs from multiple digital-to-analog converters
US9564913B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 9, 2016 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Mar 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/662
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed systems include a clock-multiplying phase locked loop (PLL) generating a clock signal for a DAC comprising a plurality of DAC cells, the systems configured to control that a phase of the DAC output has a predefined relation to a phase of a PLL input reference clock. An exemplary system incorporates an auxiliary DAC cell implemented as a replica of one of the DAC cells of the DAC and operation of the DAC and the auxiliary DAC cell is timed with the same clock signal generated by the PLL, so that outputs of the auxiliary cell and the DAC are phase synchronized by design. The system is configured to ensure that a phase of the auxiliary DAC cell output is related to the phase of the PLL reference clock, which results in a phase of the DAC output also being related to the phase of the PLL reference clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.