Power delivery network in a printed circuit board structure
US9565762B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2014 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Mar 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09536
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure provide a printed circuit board (PCB) structure. The PCB structure includes a plurality of dielectric layers including an outer layer, a second layer disposed immediately below the outer layer, at least one first power plane disposed on at least one first internal layer of the PCB structure, and at least one first ground plane disposed on at least one second internal layer of the PCB structure. The PCB structure further includes an array of buried vias passing through at least the second layer configured to respectively connect power pads disposed on the second layer to the at least one first power plane and to connect ground pads disposed on the second layer to the at least one first ground plane. The array of buried vias is defined by columns of pads in which a respective column includes either power pads or ground pads, columns of power pads alternate with columns of ground pads, and pads of at least one of a column of power pads and a column of ground pads are staggered with respect to other pads of the at least one of the column of power pads and the column of ground pads. The PCB structure further includes an array of outer layer vias passing through…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.