DRAM with SDRAM interface, and hybrid flash memory module
US9569144B2 · kind B2 · utility
7Cited by
2References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2013 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Apr 27, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.