Patent · US Active

FMA unit, in particular for utilization in a model computation unit for purely hardware-based computing of function models

US9569175B2 · kind B2 · utility

0Cited by

2References

13Claims

0Family size

Assignee

Robert Bosch GmbH · DE

Inventors

Wolfgang Fischer · Eppelheim, DE
Andre Guntoro · Weil der Stadt, DE

Key dates

Filing date	May 21, 2014
Grant date	Feb 14, 2017
Priority date	—
Expiry date	Feb 8, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG06F7/5443
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An FMA unit, for carrying out an arithmetic operation in a model computation unit of a control unit, is configured to process input of two factors and one summand in the form of floating point values, and provide a computation result of such processing as an output variable in the form of a floating point value. The FMA unit is designed to carry out a multiplication and a subsequent addition, the bit resolutions of the inputs for the factors being lower than the bit resolution of the input for the summand and the bit resolution of the output variable.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.